View UR5595G-SH2-R_1245524.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

unisonic technologies co., ltd ur5595 cmos ic www.unisonic.com.tw 1 of 12 copyright ? 2009 unisonic technologies co., ltd qw-r502-062.b ddr termination regulator ? description the utc ur5595 is a linear bus termination regulator designed to meet jedec sstl-2 and sstl-3 (stub series terminated logic) specifications for termination of ddr-sdram. the device contains a high-speed operational amplifier to provide excellent response to the load tr ansients, and can deliver 1.5a continuous current and transient pea ks up to 3a in the application as required for ddr-sdram termination. with an independent v sense pin, the ur5595 can provide superior load regulation. the ur5595 provides a v ref output as the reference for the applicati on of the chipset and dimms. the output, v tt , is capable of sinking and sourcing current while regulating the output voltage equal to v ddq / 2. the output stage has been designed to maintain excellent load regulation and with fast response time to minimum the transition preventing shoot-through. the utc ur5595 also incorporates two distinct power rails that separates the an alog circuitry (avin) from the power output stage (pvin). this powe r rail split can be utilized to reduce the internal power dissipation. and this also permits utc ur5595 to provide a termination solution for ddrii sdram. ? features * power regulating with driving and sinking capability * low output voltage offset * no external resistors required * low external component count * linear topology * low cost and easy to use * thermal shutdown protection lead-free: ur5595l halogen-free: ur5595g ? ordering information ordering number normal lead free halogen free package packing ur5595-s08-r ur5595l-s08-r ur5595g-s08-r sop-8 tape reel ur5595-sh2-r ur5595l-sh2-r UR5595G-SH2-R hsop-8 tape reel
ur5595 cmos ic unisonic technologies co., ltd 2 of 12 www.unisonic.com.tw qw-r502-062.b ? pin configuration ? pin description pin no pin name description 1 nc no internal connection. can be used for vias. 2 gnd ground. 3 v sense feedback pin for regulating v out . 4 v ref buffered internal reference voltage of v ddq /2. 5 v ddq input for internal reference equal to v ddq /2. 6 av in analog input pin. 7 p vin power input pin. 8 v tt output voltage for connecti on to termination resistors.
ur5595 cmos ic unisonic technologies co., ltd 3 of 12 www.unisonic.com.tw qw-r502-062.b ? block diagram
ur5595 cmos ic unisonic technologies co., ltd 4 of 12 www.unisonic.com.tw qw-r502-062.b ? absolute maximum ratings parameter symbol ratings unit pv in , av in , v ddq to gnd v dd -0.3 ~ +6 v supply voltage av in to gnd(note 1) v dd 2.2 ~ 5.5 v junction temperature t j +150 operation temperature t opr 0 ~ +125 storage temperature t stg -65 ~ +150 note: 1.signified recommend operating range that indicate s conditions for which the device is intended to be functional, but does not guarantee specific performance limits. 2.absolute maximum ratings indicate limits beyond which damage to the device may occur. ? thermal data parameter symbol ratings unit thermal resistance junction-ambient ja 150 /w ? electrical characteristics (t j =25 , v in =av in =pv in =2.5v, v ddq =2.5v, unless otherwise specified). parameter symbol test conditions min typ max unit v ref voltage v ref v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.135 1.235 1.335 1.158 1.258 1.358 1.185 1.285 1.385 v i out = 0a v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 v tt output voltage i out = 1.5a v tt v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 v v tt output voltage offset (v ref - v tt ) v o(off) v tt i out = 0a i out = -1.5a i out = +1.5a -20 -25 -25 0 0 0 20 25 25 mv quiescent current i q i out = 0a 320 500 a v sense input current i sense 13 na v ref output impedance z vref i ref = -30 ~ +30 a 2.5 k ? v ddq input impedance z vddq 100 k ? thermal shutdown t shdn 165 thermal shutdown hysteresis t hys 10
ur5595 cmos ic unisonic technologies co., ltd 5 of 12 www.unisonic.com.tw qw-r502-062.b ? pin descriptions av in , pv in input supply pins . av in and pv in are two independent input supply pins for ur5595. av in is used to supply all the internal analog circuits and pv in is only used to supply the out put stage to create the regulated v tt . using a higher pv in voltages will increase the driving capability of v tt , but the internal power loss will also increase. if the junction temperature exceeds the thermal shutdown than the ur5595 will enter a shutdown state, where v tt is tri-stated and v ref remains active. for sstl-2 applications, the av in and pv in can be short together at 2.5v to eliminate the need for bypassing capacitors for the two supply pins separately. v ddq the input pin used to create the internal reference voltage from a resistor divider of two internal 50k ? ? resistors for regulating v tt and to guarantee v tt will track v ddq /2 precisely. as a remote sense by connecting v ddq directly to the 2.5v rail for sstl-2 applications is an optimal implementation of v ddq at the dimm. this ensur es that the reference voltage tracks the ddr memory rails precisely with out a large voltage drop from the power lines. v sense the sense pin supply improved remote load regulation; if remote load regulation is not used then the v sense pin must still be connected to v tt . a long trace will cause a significant ir dr op resulting in a termination voltage lower at one end of the bus than the other. connect v sense pin to the middle of the bus to provide a better distribution across the entire termination bus ca n reduce the ir drop. v ref v ref supply the buffered output of t he internal reference voltage (v ddq /2). it can provide t he reference voltage of the northbridge chipset and memory. for better per formance, a bypass ceramic capacitor of 0.1 f~0.01 f, located close to the pin, can be used to to help with noise. v tt v tt is a regulated output that is used to terminate the bus resistors of ddr-sdram. it can precisely track the v ddq /2 voltage with the sinking and sourcing current capability. the utc ur5595 is designed to handle peak transient currents of up to 3a with a fast transient response. if a transient is expected to remain above the maximum continuous current rating for a significant amount of time then the output capacitor size should be large enough to prevent an excessive voltage drop.
ur5595 cmos ic unisonic technologies co., ltd 6 of 12 www.unisonic.com.tw qw-r502-062.b ? capacitor selection a capacitor is recommended for improv e input stability performance during la rge load transients to prevent the input power rail from dropping, especially for pv in . the input capacitor should be loca ted as close as possible to the pv in pin. a typical recommended value for al electrolytic capacitors is 50 f and 10 f with x5r for ceramic capacitors. if av in and pv in are separated, the 47 f capacitor should be placed as close to possible to the pv in rail. an additional 0.1uf ceramic capacitor can be placed on the avin rail to prevent excessive noise from coupling into the device. utc ur5595 has been designed to be insensitive of output capacitor size or esr (equivalent series resistance). the choice for output capacitor depends on the application and the requirements for load transient response of v tt . as a general recommendation the output capacitor should be sized above 100 f with a low esr for sstl applications with ddr-sdram. the value of esr should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. ? thermal dissipation the ur5595 will generate heat result from internal power dissipation when current flow working. the device might be damaged any beyond maximum junction temperature rati ng. the maximum allowable internal temperature rise (t rmax ) can be calculated given the maximum ambient temperature (t amax ) of the application and the maximum allowable junction temperature (t jmax ). t rmax = t jmax ? t amax from this equation, the maximum power dissipation (p dmax ) of the part can be calculated: p dmax = t rmax / ja the ja of ur5595 can be calculated (refer to jedec standard) and will depend on several package type, materials, ambient air temperature and so on.
ur5595 cmos ic unisonic technologies co., ltd 7 of 12 www.unisonic.com.tw qw-r502-062.b ? typical application circuits following demonstrate several different application circuits to illustrate some of the opt ions that are possible in configuring the utc ur5595 . the individual circuit performance can be found in the typical performance characteristics that curve graphs illustrate how the maximum output current is affected by changes in av in and pv in . stub-series terminated logic(sstl) termination scheme sstl was created to improve signal integrity of the data transmission across the memory bus. this termination scheme is essential to prevent data error from signal re flections while transmitting at high frequencies encountered with ddr-sdram. the most popular form of termination is class ii single parallel termination. it involves one r s series resistor from the chipset to the memory and one r t termination resistor (refer to figure 1). r s and r t are changeable to meet the current requirement from ur5595, the recommended values both r s and r t are 25 . figure 1. sstl-termination scheme for sstl-2 applications for the majority of applications that implement the sstl- 2 termination schem e, it is recommended to connect all the input rails to the 2.5v rail as figure 2. this provides an optimal trade-off between power dissipation and component count and selection. figure 2. recommended sstl-2 implementation
ur5595 cmos ic unisonic technologies co., ltd 8 of 12 www.unisonic.com.tw qw-r502-062.b ? typical application circuits(cont.) figure 3 illustrate another a pplication that the power rails are split when power dissipation or efficiency are concerned. the output stage (pv in ) can be as lower as 1.8v, and the analog circuitry (av in ) can be connected to a higher rail such as 2.5v, 3.3v or 5v. this allows the internal power dissipation to be lowered when sourcing current from v tt , but the disadvantage of this circuit is the maximum continuous current is reduced. figure 3. lower power dissipation sstl-2 implementation the third optional appl ication is that pv in connect to 3.3v and av in will be always limited to operation on the 3.3v or 5v to always equal or higher than pv in . this configuration has the ability to provide the maximum continuous output current at the downside of hi gher thermal dissipation. the power di ssipation increasing problem must be careful to prevent the junction temperature to exceed t he maximum ranting. because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3v rail. figure 4. sstl-2 implementation with higher voltage rails
ur5595 cmos ic unisonic technologies co., ltd 9 of 12 www.unisonic.com.tw qw-r502-062.b ? typical application circuits(cont.) for ddr-ii applications as a result of the separate v ddq pin and an internal resistor divider, ur5595 can be utilized in ddr-ii system, figure 5 and 6 show two recommended circuits in ddr-ii s dram application. the output stage is connected to the 1.8v rail and the av in pin can be connected to either a 3.3v or 5v rail. if it is not desirable to use the 1.8v rail it is possible to connect the output stage to a 3.3v rail. the power dissipation increasing concern must be careful as well sstl-ii application. the advantage of configuration of figure 6 is that it has the ability to source and sink a higher maximum continuous current. + + + v tt v ddq v sense v ref gnd av in pv in c in v ddq =1.8v av in =2.2v 5.5v c out c ref v ref =0.9v v tt =0.9v utc ur5595 pv in =1.8v figure 5. recommended ddr-ii termination figure 6. ddr-ii termination with higher voltage rails
ur5595 cmos ic unisonic technologies co., ltd 10 of 12 www.unisonic.com.tw qw-r502-062.b ? typical characteristics 1.40 1.10 -30 -20 0 10 20 30 i ref ( a) v ref vs. i ref 1.35 1.30 1.25 1.20 1.15 -10 3 2.5 2 1.5 1 0.5 0 012 3456 v ddq (v) v ref vs. v ddq 1.275 1.270 1.265 1.260 1.255 1.250 1.245 -100 -75 0 25 75 100 i out (ma) v tt vs. i out (0 ,25,85,and 125 ) -50 -25 50 125 0
ur5595 cmos ic unisonic technologies co., ltd 11 of 12 www.unisonic.com.tw qw-r502-062.b ? typical characteristics(cont.)
ur5595 cmos ic unisonic technologies co., ltd 12 of 12 www.unisonic.com.tw qw-r502-062.b utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

▲Up To Search▲

Price & Availability of UR5595G-SH2-R

	To Download UR5595G-SH2-R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .